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www.play-hookey.com | Fri, 12-06-2019 |
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Direct Current
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Alternating Current
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Semiconductors
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Digital
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Logic Families
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Digital Experiments
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Computers
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| Analog | Analog Experiments | Oscillators | Optics | HTML Test | |
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| Combinational Logic | Sequential Logic | Alternate Flip-Flop Circuits | Counters | Registers | The 555 Timer | | ||
| D Flip-Flop Using NOR Latches | D Flip-Flop Using NAND Latches | CMOS Flip-Flop Construction | |
Alternate Flip-Flop Circuits |
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The latch and flip-flop circuits we've seen so far were mainly constructed from NAND gates, with the input configurations changed according to the flip-flop type. The flip-flop circuits also used separate four-gate latch circuits for the master and slave sections. However, this is not the only possibility; there are a number of alternatives.
Here's an edge-triggered D flip-flop that will always take on the state of the D input at the falling clock edge, regardless of how many trasistions have occurred at the D input.
This edge-triggered D flip-flop is identical to the NOR version, except that it uses NAND gates. The difference in behavior lies only in which clock edge will enable the output to change state.
CMOS technology makes some very interesting variations possible.
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