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| D Flip-Flop Using NOR Latches | D Flip-Flop Using NAND Latches | CMOS Flip-Flop Construction |

The latch and flip-flop circuits we've seen so far were mainly constructed from NAND gates, with the input configurations changed according to the flip-flop type. The flip-flop circuits also used separate four-gate latch circuits for the master and slave sections. However, this is not the only possibility; there are a number of alternatives.

D Flip-Flop Using NOR Latches

Here's an edge-triggered D flip-flop that will always take on the state of the D input at the falling clock edge, regardless of how many trasistions have occurred at the D input.

D Flip-Flop Using NAND Latches

This edge-triggered D flip-flop is identical to the NOR version, except that it uses NAND gates. The difference in behavior lies only in which clock edge will enable the output to change state.

CMOS Flip-Flop Construction

CMOS technology makes some very interesting variations possible.

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